RF dividers are one of the crucial building blocks in RF PLLs since they operate at the speed of the RF oscillator. Typically RF dividers are done by an even number of synchronous D-flip-flops clocked with the same differential signal. This allows to obtain frequency dividers with an even numbered division factor n and 2n equidistant phases. Particularly, the phase of quadrature output signals (differential I/Q) is important. This quadrature phases are obtained by a synchronous divide-by-2 circuit with 4 outputs. For odd division factors these structures cannot be used.
RF dividers based on synchronous flip-flops are well known. They consist of a chain of a number of n flip-flops clocked with opposite signals. The resulting output has 2n signals at equidistant phases with 1/n th of the input frequency. A typical standard RF flip-flop for this purpose is shown in FIG. 1. (In the literature exist many variations of this structure e.g. the PMOS load can be replaced by a resistor.) The flip-flop has two differential clock inputs C, C, two differential inputs I,Ī, and two differential outputs O,Ō. The clock inputs are sensitive to the rising edge of a clock input signal.
The switching behavior of this flip-flop is shown in the following table 1.
TABLE 1IĪC COnŌn10 1010 On−1Ōn−101 0101 On−1Ōn−1
The flip-flop is set and reset by the rising clock edge. A prior art divide-by-2 circuit based on these flip-flops is shown in FIG. 2. These kind of architectures allows to make even number dividers only. Therefore the 2n outputs of these divide-by-n circuits always contains quadrature phases.
It is known in the art to obtain a quadrature signal at ⅓n of the input frequency by using a regenerative divider (see below) in combination with a conventional divider, see e.g.:
U.S. Pat. No. 6,785,528: “Quadrature Divider”; quadrature divider done as a regenerative divider allowing for division factors of M/(M±1).
WO 2004064246: “Regenerative Divider for Up and Down Conversion of Radio Frequency (RF) Signals”; regenerative divider allowing for up conversion by a factor of 4/3.
The possibility to obtain a quadrature signal at fractions of the input signal by using regenerative dividers is known and possible (see e.g. references cited above). In the case of a desired quadrature signal at ⅓ of the input frequency, this architecture requires the use of a divide-by-2 circuit in the feedback loop of the divider in order to get a signal at ⅔ of the input signal and another divide-by-2 circuit at the output in order to get ⅓ of this frequency.
Since regenerative dividers are basically mixers where the output frequency is fed back (divided by an integer) to the second mixer input, they always produce two mixing products (lower and higher sideband). Therefore it is necessary to remove the unwanted sideband to get only one frequency at the output. This can be done by using single sideband mixers, which require an I and a Q signal at both inputs and the output of the mixers, by using a notch or low pass filter in the mixer output or by using a poly-phase filter in the feedback path. Due to the use of mixers and filters, many of the regenerative dividers operate with sinusoidal outputs.
Therefore the outputs are relatively sensitive to jitter produced by noise (as opposed to pulses with steep slopes). Moreover they often operate at relatively small amplitudes which makes them sensitive to noise (low signal to noise ratio).